B3G Research On Key Technology

In order to achieve a reliable communication over wireless channels, error correction codes should be used in communication systems. Low density parity check (LDPC) code, which is a special case of error correction code with sparse parity-check matrix, has the performance very close to the Shannon Limit. The properties of LDPC code are low complexity and high throughput. Due to the excellent performance, LDPC code has been studied with more and more attentions. However, the effective hardware implementation of a LDPC decoder becomes a crucial issue in practical systems.With the development of mobile communication technology, the study of beyond 3G mobile communication system has entered design and implementation phase. In order to satisfy the need in a variety of services and the high data rate, LDPC code is used for channel code in the B3G-system. The purpose of this thesis is to study the hardware architecture of LDPC decoder in B3G-system and the FPGA implementation scheme.Following a short background introduction of channel coding, the thesis describes LDPC code and decoding algorithm. Min_Sum algorithm is used for the decoder of the architecture in this paper, due to low complexity.Three decoder architectures, parallel, serial and partially-parallel approaches, are analyzed in this thesis. A kind of novel partially-parallel architecture for decoding LDPC code is proposed. The trade-off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially-parallel architecture for the random parity check matrix. By column exchanging, the (m, n) parity check matrix is divided into k (m, ni ') sub-matrixes which obey the same rules. The decoder processes messages in parallel mode between k sub-matrixes, but the serial mode is used in sub-matrixes decoding.In B3G-system, the LDPC code has been used with the random irregular parity-check matrix, which the data length is 3944. The LDPC decoder, described in the Verilog HDL, has been implemented with Xilinx FPGA device Virtex-ⅡPro70. The maximum throughout of this decoder is 6.5 Mbps with 20 iterations. This design is...