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Key Technology And Verification Of 800Mbps Throughput Parallel Coding And Decoding For LDPC Code

Posted on:2018-10-20Degree:MasterType:Thesis
Country:ChinaCandidate:G WangFull Text:PDF
GTID:2348330515451678Subject:Communication and Information System
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With the increasing requirement of bandwidth and rate of wireless communication,it is more and more difficult to deal with baseband signal on hardware.Because of its good performance,LDPC codes have been widely used in broadband wireless communication.However,it is still the focus of the research that how to realize the LDPC encoding and decoding and improve its performance as much as possible under the condition of limited hardware resources and time resources.This paper study the implementation of 7/8LDPC encoding and decoding in CCSDS standard that used in a communication link which its rate is 800 Mbps,and the bandwidth is 600 MHz.The main contents is as follows.First,this paper analyzes the challenges of hardware implementation of LDPC encoding and decoding in high speed data transmission based on the present situation of LDPC encoding and decoding technology.This subject is to achieve the OFDM high-speed digital baseband prototype.According to its frame structure and rate requirements,the paper analyzes the concrete difficulties of LDPC encoder and decoder.Second,the paper designs and implements LDPC encoder with a rate of 800 Mbps.It gives a detailed design of the encoder,including the overall structure of the encoder and the specific design of the input subframe module,subframe coding module and output frame module.The problem of the generator matrix that should be saved in the process of coding is solved properly.Using modular design and streaming operation make the encoder efficient and resource saving.Third,the paper designs and implements LDPC decoder with a rate of 800 Mbps.It gives a detailed design of the program,including the overall structure of the decoder and the module division and the specific design of each submodule.And a good plan is proposed to save the parity check matrix during the process of decoding.Finally,we put the LDPC encoder and decoder in the FPGA to test the performance.This paper designs and realizes the 800 Mbps throughput parallel encoding and decoding of LDPC codes,which has a certain role in promoting the application of 7/8LDPC codes in CCSDS standard.In order to solve the problem of matrix storage in the process of encoding and decoding,it is of great practical significance to put forward an effective and simplified scheme.
Keywords/Search Tags:Low Density Parity Check Code, high speed data transmission, parity check matrix, generator matrix
PDF Full Text Request
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