.51 Nuclear Soc Application Design

System-on-a-Chip(SOC) is a complex integrated system. It is impossible for a designer to complete the reliable and optimum implementing without intellectual property (IP) reuse within the limited time. Moreover, SOC design process involves many theories and applications such as Signal and System, Integrated Electronics, Layout, Semiconductor Technology, Verification Algorithms, etc. Hence, in order to master the SOC frame and analysis method, standardize the design flow, and obtain the scheme for micro-controller based SOC plan, it is necessary to study the SOC design approach based on DW8051 IP core.The SOC design approach and analysis method based on DW8051 IP core are employed in this thesis for the intelligent IC card telephone application. This research project focuses on the IP reuse, IP transplant and design verification in the SOC design.The thesis begins from the simple description of SOC and its present status. Then, the external interface, interface timing and data structure of DW8051 IP core are illustrated in detail according to MCS-51 signal chip. Afterwards, the peripheral modules have been framed and designed from system level to register-transmission-logic (RTL) level according to the IC card telephone application. Finally, the logic synthesis methodology, static timing analysis strategy and prototype emulate are proposed and used for the analysis of simulation results.The main results are listed bellow:1. The intelligent IC card telephone SOC structure is investigated in detail.2. The logic synthesis process is studied in detail and the relative constraints are discussed.3. The SOC timing path is investigated in detail for static timing analysis.4. The test-bench has been developed to verify the SOC design.This dissertation is partially supported by Chengdu Goldtel Microelectronics Co., LTD. This research results have been used in production and meet the...