Mixed PTL/static logic synthesis using genetic algorithms: Theory and applications

With the increasing demand of high-performance and high-density VLSI (Very Large Scale Integrated circuits) designs, technology scaling has been meeting the increasing demand and will continue in UDSM (Ultra Deep-SubMicron) regimes. As the complexity of a chip increases almost exponentially as CMOS (Complementary Metal-Oxide Semiconductor) technology scales to under 100 nm, the difficulty of designing VLSI system has increased. Thus, the gap between design productivity and technology capability is increasing. Because of this gap, efficient and practical EDA (Electronic Design Automation) solutions have become more and more relevant in ensuring successful chip designs and time-to-market.; Static CMOS logic style has long been used widely to realize a VLSI system because of ease to use and well-developed synthesis methods. With power becomes an increasingly limiting factor in high density and high-performance VLSI designs, a great deal of effort has been made to explore low-power design options without sacrificing performance. Pass-transistor logic (PTL) is being considered as an alternative logic style of static CMOS because static logic consumes a large amount of power due to large short circuit current. Generally, PTL consumes less power than static logic because of its small capacitive load and smaller area. However, PTL only circuits would increase the circuit delay caused by a long transistor chain in series.; In this dissertation, a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method is presented. The main advantage of mixed PTL/Static circuits is that the static CMOS acts as a buffer as well as performs a logic function. The proposed synthesis method searches for possible matches between a logic structure and a set of predefined PTL/Static logic gates using Binary Decision Diagrams (BDDs). This proposed mixed PTL/Static synthesis method also optimizes the final mapped circuits on a global level by using genetic algorithms (GAs). Our experimental results demonstrate that circuits synthesized using our proposed mixed PTL/Static synthesis method outperform their static counterparts in delay or power consumption, or both in various CMOS technologies. The impacts of technology scaling on mixed PTL/Static circuits in terms of performance and power consumption are also examined by means of both theoretical projections and experiments. The projection and experimental results give more evidence that the mixed PTL/Static circuit style is a promising alternative to static and domino circuit styles for high-performance and low-power applications in the future.