The Pico Dedicated Microcontroller Core Design For Testability

With the developing of VLSI, especially the wide adoption of high speed memory chips, ASIC and programmable ICs, function of many electronic systems such as PC has been dramatically improved. But on the other hand, the difficulties in testing these systems are keeping growing. Conventional external function test is no longer adoptable.To solve such a difficult problem, many theories and technologies came out in IC industry. The so-called Design-for-Test (DFT) is the methodology of considering the need of testing in the early stage of system design, and, by adjusting the system architecture and adding some testable mechanism, improving the controllability and observability, and finally facilitating the system testing.In this paper, this thesis started with studying of the basic concepts of IC testing, analyzed and compared some central problems. Then it described a model of synchronized digital logical circuit and its DFT design. In the following chapter5, the theories and principles of scan-chain based DFT design were discussed. In the ending part of this paper, this thesis used EDA tools to accomplish the DFT design task of an embedded MCU core, checked and analyzed the design results.