Embedded Microprocessor Design For Testability And Implementation

With the development of 1C desinging and manufacturing technology, the chip' s density and complexity also rises with the astonished rate. The testing of the chip is faced with very serious challenge, the cost of testing is always rising, and even larger than the designing and manufacturing cost. Especially with the use and advancement of VDSM(Very-Deep-Sub-Micron) technology, the faults during manufacturing become more multiple and difficult to test. " With the circumstance of all these things, l)FT(Design-For-Testability) technology become one of the main means to cult with the problem of chip manufacturing test and attract more and more attention.Design For Testability means adjusting the structure of circuit and making the circuit easy to test. In this paper we investigate and carry out boundary scan ^ internal scan and built-in self-test three DFT technologies in the embedded microprocessor Estarl and get satisfying result, the fault coverage is more than 96%.Boundary scan aims at the test of application system, e.g. PCB test. International standard IEEE 1149. 1 describes the basic circuit structure and performance of boundary scan. In this paper, we combine the standard modules realize the boundary scan of Estarl and also expand it to the test of internal circuit. This structure can save the I/O port of the chip and simplify the testing program.Internal scan is advanced for the difficulty of fixing the state of sequential circuit, can be divided into full-scan and partial-scan. In this paper we use full-scan according to the real circumstance of Estarl and get high fault coverage with very little impact on the circuit.Bult-In Self-Test is considered to be the most hopeful technology to solve the great cost and difficulty of manufacturing test because of the increasing of the circuit density. In this paper we use the BIST in the testing of the SSRAMs in Estarl according to the characteristics of the structure and get almost 100% fault coverage.The rapid development of System-on-Chip(SoC) technology has been attracting more and more attention in computer and electronic engineering domain these years. The test of SoC is special and complex because the use of the IP core. In this paper, we investigate the problem of SoC test and introduce embedded core test international standard IEEE P1500.