Embedded Soc Debug The Design Of The Study

More circuits can be integrated on a chip along with the development of IC technology, and the single chip system comes out which is called system on chip (SoC). The appearance of SoC makes a chip have more complex function and get higher performance, but also makes the observation and controllability to the internal signals of a chip difficult. Adding the DfD (Design for Debug) to improve the observability and controllability of SoC becomes more and more important.On the other hand, developing embedded system on SoC need to control and observe the program running on chip. It means debug can not impact the execution of program and not occupy any system resources. Because the resource of embedded system is limited, the debug usually adopts a cross-way. That means the debug software runs on PC host and it connect to the target debug interface with some cable. Through this way, it only needs a debug interface on target with less resource requirement.This paper introduces the RISC32E IP core which is developed by SoC R&D group of Department of Information Science and Electronic Engineering in Zhejiang University, and it introduces the design of JTAG debug interface on RISC32E and the debugger on PC. This JTAG debug scheme adds some debug exceptions which can be used to control the program running on processor, including debug interrupt, single step, software breakpoint, hardware breakpoint and so on. A Debug Mode is added to processor in which the debug host can access the registers and memories on chip through JTAG port. So the processor's status can be observed and it meets the requirement of observability. Additionally, in order to improve the transfer efficiency on JTAG port, a fast transfer method is designed. This method can transfer data between PC host and target memory faster. Through this way, the time on data transfer is saved and debug can be more efficient. To use the JTAG debug interface, a debugger based on command line is developed on PC. It runs on PC and can access JTAG port through the protocol converter wiggler from parallel port to JTAG. The debugger can receive commands from command line and parse them to call obverse function, then change the function to JTAG signals and achieve the controllability to target.Maybe there are more than one IP cores to be debugged on SoC, and only one JTAG port can be used to debug. This paper introduces a scheme with multi model JTAG inter-connect, which is compliant to IEEE 1149.1 protocol, and supports both single core debug and multi-core debug. This scheme can reuse the IP core debug interface and its debug software in multi-core environment, it's low-cost and can meet the basic need of multi-core debug.