A Test Method Study On Single Chain Full Scan Structure Based On IEEE P1687 Network

The characteristics size of a chip is getting more and more smaller, as the manufacturing technology of integrated circuit has entered the deep sub-micron level. More and more functional module can be integrated on a single chip and the system is becoming increasingly complex. Traditional top-down chip design method that depends on the engineer's experience has already can not adapt to rapidly changing market demand. SOC(System On Chip) System based on IP(Intellectual Property) core reuse technology arises at the historic moment.The introduction of the IP core reuse technology saves SOC chip development costs, shorten the time of the product. However, as design and manufacturing technology progress, the development of the chip testing technology is relatively slow. Chip-level interconnection test standards based on the probe contact measurement adopted by the past, such as IEEE1149 standard, cannot meet the demand of system chip SOC test any more. Because the chip package used today are normally flat package or ball grid array and the pins are no longer exposed.After studying the IEEE1687 standard, on the basis of combination of design for test theory, in this paper, an SOC chip single chain full scan design method based on the standard is put forward for solving embedded core test problem,by defining the standard access control interface modules of SIB, increasing the SIB interface between different levels and access mechanism, using the procedural description language specification testing process at the same time.In this paper, concrete work done is as follows:1) Refer to a large number of related literature at home and abroad, to determine the SOC chip test development present situation and research meaning.2) Analysis the relationship and difference between current different chip test standard, combine the basic theory of design for test, define the specific function of each branch module based on standard IEEE1687 SOC chip design test framework. Design and implement the encapsulation of embedded IP core shell, standardize the SIB(Segment Insert Bit) switch interface that can be used to access route between chip level.Accomplish coding the state machine, the custom instruction code and interface specification.3) Through the configuration of the corresponding register, loading different instruction, implement the effective access to and control of embedded IP core. Using the VCS(Verilog Compiled Simulation) Simulation software to verify the correctness of the design circuit function.4) Combined with SOC chip testability design, points out the shortage of this subject as well as the main direction of future development.Simulation results show that through the JTAG(Joint Test Access Group) interface, the key register of each IP core can be configured.It realizes scanning path selection and flexible switch, completes the configuration and test for different levels of SOC chip module. The expected goal is achieved by the basic function correctness and feasibility that approved.The design scheme of strong extensibility, can very well deal with different compatibility of embedded IP core manufacturers, accelerate the development of SOC test process standardization at the same time.