Design Of 1553B Bus Interface Based On FPGA

With the rapid development of electronic technology and computer, the technologyof data bus is improved constantly. As a high reliability bus technique, 1553B-bus is usednot only in military but also in civil more and more widely. MIL-STD-1553B is a credibledata bus with high transmission reliability. It especially used in the key computer modulewhich realizes the communication between the real-time sensor and the control unit.This paper puts forward a method of designing the interface based on FPGA afterstudying the 1553B protocol and the design of foreign chip product. Combining theEDA technology and the trait of large programmable logic device. The paper putsforward a project of design the interface based FPGA.Firstly, According to the detailed function of interface chip, this paper apply theTop-Down designing method to put forward the total design scheme 1553B businterface. And then according to the function’s implementing divide the structure ofthe design.Secondly, This paper primary introduces the design of BC/RT/MT terminal, andthen gives the design,simulation and testing of important modules. Criticaltechnologies are applied. The paper describe the design VHDL, synthesis by synthesisand realize it in FPGA.Finally, design the test system of bus interface chip, and select theTMS320LF2407 as the primary CPU. The test contain the self-receiver & self-transmitter of the CPU, and the RS232 serial debug to hence the intuition of test data,The result of validate indicates that the design in this reasonable and right.