The Design Of Radar Timing Control And Preprocessing Module Based On FPGA

The radar system occupies an important position in the modern military-field.To ensure the normal operation of the radar system,a stable and accurate time sequence is needed.The preprocess must be performed on the receiving radar echoes to complete the analog-todigital conversion and digital down conversion(DDC).Meanwhile,to relieve signal processing pressure,the data rate of radar echoes should also be reduced.In this thesis,the research background and significance of radar timing control and preprocessing modules are firstly described.The applications of FPGA and CPU in modern radar system are respectively introduced.Thereafter,based on the comprehensive renovation project of a certain type of radar,an integrated system led by FPGA+CPU at its processing core is designed to complete signal and data processing.In this system,FPGA is utilized to complete the timing control and data preprocessing of radar system,and the CPU is responsible for signal and data processing.With respect to the designed system,the hardware platform and board assignments of signal and data processing module are briefly introduced.On the other hand,the detailed design of AD sampling and timing control board(AD board)is introduced,which is the hardware platform of the timing control and preprocessing module.In the third chapter,the implementation principles and design ideas of the main functional sub-modules are described in detail.Then the measurement data is adopted to analyze the sampling performance of the AD sampling chip,and the simulation data is used to verify the digital down conversion module.Furthermore,the comparative analysis of the processing results between FPGA and MATLAB are also given.In the integrated system,there are multiple data communication interfaces between the AD board and other boards.In this chapter,the transmission protocols of the PCI Express interface,Gigabit Ethernet interface,and serial port are briefly described respectively,and their implementation methods are introduced one by one.The overall implementation of the timing control and preprocessing module on the AD board are described in the fourth chapter.For the subsystems of radar system,such as the monitoring,terminal,transmitter and receiver,the interface communication methods and communication content between the AD board and these subsystems are presented in this paper,and the connection locations of these interfaces are listed.In the overall realization process of the timing control module,the switching process of radar system in the working pattern is firstly introduced.Thereafter,the overall timing of radar system and sequential design of all modules among the FPGA are described.The fulfillment process of preprocessing module,is designed combined with the radar signal processing flow.Furthermore,the data communication method and communication format between the AD board and the signal processing board are also explained.The design scheme in this thesis has well completed the task of radar timing control and preprocessing,and explored the application of FPGA+CPU system architecture in radar system.Through the integrated system of signal and data processing in this project,the stability and signal processing performance of radar system is improved,and the automatic tracking acquisition and fine processing methods are realized.Moreover,the software level of radar system is also enhanced.