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Research On The Transmission Interface And Key Techniques Of A Large Capacity ATM Switch Based On FPGA

Posted on:2010-11-20Degree:MasterType:Thesis
Country:ChinaCandidate:W QiuFull Text:PDF
GTID:2248360302991345Subject:Communication and Information System
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SDH technology has the advantages of high speed, large capacity, efficient resources utilization, and low costs of management and maintenance. The products based on SDH technology is widely used in existing access networks and core networks, and found huge prospect. China is still relatively weak in the research and manufacture of SDH chips. We can understand the implementation principles of internal modules in SDH chips and produce the own Intellectual Property (IP) core if we throughly study on the issues of commercial SDH chips, such as its functions, the hardware & software configurations, and the implementation of its communication interfaces by FPGA. Meanwhile, these studys can not only provide initial technical foundation for developing homemade SDH chips and other communication network chips, but also have important practical value.Sponsored by the project named the prototype of ATM switching on-board with 10Gbps large capacity, this dissertation focuses on investigating the functions of main internal modules in the SDH line interface chip, and completes the implementation of the hardware configurations and software driver program. The inter-module interfaces in the switch use the specifications of UTOPIA Level 3 and UTOPIA Level 1, two of which are defined by ATM forum and the second is revised little. Based on Xilinx Virtex-II FPGA, this dissertation implements the functions of the two interfaces through VHSIC Hardware Description Language (VHDL) codes and completes the simulation. The hardware and software for the SDH chip and the UTOPIA interface are all tested within the prototype switch, and the result shows that they have proper functions and meet the design requirements. In addition, this dissertation also explores adding the cell-priority management and scheduling functions to the UTOPIA interface, and completes the simulation and verification of such two functions by FPGA. Finally, the issues to be studied further are also proposed with the summary of whole dissertation.
Keywords/Search Tags:Universal Test & Operations PHY Interface for ATM (UTOPIA), Synchronrous Digital Hierarchy (SDH), Line Interface, VHSIC Hardware Description Language (VHDL), Field Programmable Gate Array (FPGA)
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