Logic Synthesis And LEC Verification Of LTE Module Based On 28nm

With rapid development of the integrated circuits,the requirements of digital chip for logic synthesis and logical equivalence checking are becoming more and more higher.There is an urgent need to find suitable solutions.Based on the technology of 28 nm,this paper chooses two very large scale integrated circuits from the LTE of a digital chip and compares three synthesis methods and two equivalence checking methods.Finally,this paper finds the most excellent logic synthesis method is DCG and optimum equivalence checking method is Hierarchy,and it also introduces the design check into the synthesis process.First of all,with the help of a comprehensive tool-Design compiler,this text uses three methods including DCG,DCT and DC to achieve logical synthesis.Systematically,this paper compares the netlists got from these three synthesis methods in the performances,such as power consumption,area and speed.Finally,this paper concludes that the netlist got from DCG is the best one.The synthesis method of DCG prepares a better gate-level netlist for physical design and reduces the cost and power.Secondly,at the end of the synthesis process,this paper executes the design check for the gate-level netlist,RTL code,and synthesis process.By checking sixteen items including the design code risks,area performances,and error reports or warnings and so on,it effectively reduces the iterative cycle of the design,saves error feedback time,and reduces the synthesis hidden errors.Besides,the design check improves the reliability of the front-end code and the physical design.Then,with the logical equivalence checking tool-Conformal LEC,this paper uses two methods including Hierarchy and Flatten to do the logical equivalence checking between RTL code and netlist.Finally,by Comparing performances such as CPU time,Memory size,and debugging time of these two methods,this paper gets the results that the method of hierarchical logic equivalence checking is the best.For hierarchy,the whole complex design will be divided into many small logic blocks,and these blocks are verified separately.For flattening verification,the design will be flattened to a complex design.When the logic circuits are not equal or abort,in the debugging stage,the hierarchical way can only check unequal or abort places.But the flatten way will check the whole design at the same time.Ultimately,With short debugging time and high efficiency,the hierarchical way can save the verification time and ensure the physical design accomplish smoothly.Finally,this paper compares the results of three synthesis methods and two LEC methods for another very large scale integrated circuit from LTE.For these two integrated circuits,this paper gets the same results.Thus,it can draw a conclusion that the accuracy of the results obtained in this paper and the paper?s reliability are improved significantly.