Design Of 1553B Bus Transaction Level Model Based On Systemc

With the increasing scale of integrate circuit, the performance of the circuits has been improved but new challenges are brought to IC design and verification. In the traditional VLSI design flow, hardware and software are carried out separately. And the software often falls behind the hardware. When the system designers integrate the HW and SW, they have to do the same work above again and again due to the modifications of the design. This leads to a waste of time. For the verification of So C, when designers do the hybrid simulation of SW and HW, the low simulation speed will cause design work behind the schedule. It is unbearable for the IC company updating it’s products quickly to seize the market. In order to solve the problems, system designers can start by using System C for Electronic System Level design(ESL),design the HW and SW at the same time. Design each module by using the approach of transaction-level modeling(TLM),it will bring shorter design cycles and faster simulation speed. After do the Co-Verification of SW and HW, designers can translate the SW code and HW code to High-level language and HDL, leads to reduce the design time.This design of the 1553 B bus TLM model is a part of the transaction-level So C verification platform. It can be used to verify the IP core of 1553 B bus quickly. This dissertation used the System C TLM2.0 standard to build the bus model, so that the communication between modules is more standardized. The dissertation firstly introduced the application background and development status of 1553 B bus, explained the importance of modeling it’s TLM model. Secondly it raised the overall program of modeling the 1553 B bus, designed the Bus Controller Interface, Remote Terminal Interface, and the channel of TLM bus. After completed the design work of 1553 B bus model, this paper built the testing system and give two schemes to test the bus model. The first scheme is testing the known function points manually and the second scheme is using the automatic test program to evaluate the simulation speed of the bus model. Thirdly integrate the 1553 B bus model and the LEON3 So C verification platform together. Finally mount the DES IP core at the 1553 B remote terminal and complete the verification work of the 1553 B bus model. The results indicate this 1553 B bus TLM model complete the communication with the So C verification platform successfully and have a faster simulation speed than the RTL model. It can be used to verify the IP core of 1553 B bus quickly.