Design Of SPARC V8Based Transaction Level SoC Verification Platform

With development of IC manufactural capacity, the design size of SoC grewrapidly. In traditional SoC design flow, embedded software must be developed basedon RTL SoC verification platform. However, due to the limitations of RTL modelsimulation mechanism, the simulation will consume a long time for larger design. Toaddress this issue, we need a higher level of modeling methods to completemodeling SoC verification platform. The verification platform can ensure the correctfunction as a prerequisite to speed up the simulation, and provides a virtualverification for the SoC system level verification and embedded softwaredevelopment before complete modeling RTL SoC verification platform.In this paper, to meet the need of SoC architecture design and embeddedsoftware development, using transaction-level modeling approach and SystemC forcompleting the SPARC V8based transaction level SoC design verification platform.First introduced SystemC based transaction level modeling approach and proposedoverall design of transaction level SoC verification platform. Then completetransaction level modeling for each of the basic components. To reduce the designcomplexity and improve the simulation speed, model the SPARC V8ISS based onthe explanation-execution technology and model devices such as AMAB bus, timer,interrupt controller, UART based on the hierarchical channel mechanism inSystemC.After completing modeling and integration of the SPARC V8based transactionlevel SoC verification platform, building test platform and design verificationprogram according to enumerative functional verification points. Using the crosscompiler to compile the validation process to get test stimulus, and using theModelSim to carry on the simulation. The results indicate the functional correctnessof the transaction level SoC verification platform. Finally testing simulation speedof transaction level SoC verification platform and RTL SoC verification platformwith the benchmark named Mibench. The results indicate the simulation speed oftransaction level SoC verification platform is2to3orders of magnitude faster thanRTL SoC verification platform, which can effectively shorten the development cycleof the whole SoC.