Research On Ultra High Speed Clock Recovery IC For Optical-Fiber Transmission System

With the rapid development of the telecommunication technology, optical communication system has become hot research point. High-speed integrate circuits for optical transmission system have drawn even more interests. As the key component of optical transmission system, the speed of clock recovery circuit (CRC) largely limits the maxmum system speed. So the high-speed CRC is the most attractive research task.The fundamental theorem of CRC and phase-locked loop (PLL) was discussed. The behavior simulation model for PLL is developed. The noise issue of CRC has involved in research work. Particularly the noise model of PLL is discussed in detail. Several key issues of super-high speed IC design, such as the parasitic model of interconnection, the behavioral analysis of transmission line and high-frequency compensation technique, were discussed in this paper.Theroy of injection PLL has been researched and an injection PLL type clock recovery circuit is designed and realized by using OMMIC's 0.2μm GaAs PHEMT technology. The measured rms jitter of extracted clock signal of preprocess circuit is 1.18ps with pseudorandom bit sequences of 223-1 at the bit rate of 9.95328 Gb/s. The measured rms jitter of recovered clock signal of CRC is 1.6ps under the stimulation of a 223-1-bit-long pseudorandom bit sequence at the bit rate of 8.2 Gb/s.Research of charge-pump PLL has involved and a 5 Gb/s monolithic clock recovery circuit is designed and realized by using 0.18μm CMOS technology. A half rate bang-bang phase detector and a four-phase current-controlled ring oscillator incorporated with a charge-pump build up half-rate PLL architecture. The measured rms jitter of recovered clock signal is 4.7ps under the stimulation of a 211-1-bit-long pseudorandom bit sequence at the bit rate of 5 Gb/s.Research of 40 Gb/s super high-speed CRC has involved in this paper. A 40 GHz monolithic phase-locked loop and a 40 Gb/s monolithic CRC are designed by using 0.2μm GaAs PHEMT technology. The phase noise of PLL is–88.83 dBc/Hz at 10kHz offset. The measured rms jitter of recovered clock signal of CRC is 1.68 ps under the stimulation of a 1010 sequence at the bit rate of 9.25 Gb/s.In summary, several creative works have been done in this paper. 5-10 Gb/s monolithic CRC were designed and it achieved the best test results domestic. A 40 GHz PLL circuit and a 40 Gb/s monolithic CRC were designed and realized, and it cover the blank of this rearch area domestic.