Research On Key Technologies Of High-Speed Interconnect Transmission In Three-Dimensional Integration Systems

With the development of semiconductor technology,the research and design of advanced technological processes has entered a stage restricted by physical limits,and the continuation of Moore's law is in great difficulties.Three dimensional(3D)integrated advanced packaging technology has become a key technology to improve the high-speed information transmission performance in and between chips further.3D multichip heterogeneous integration technology based on through-silicon via(TSV)is an important part of advanced packaging technology.TSV is based to form a stacked packaging structure with a vertical interconnection among multiple chips,which overcomes the technological limitations of planar integration and achieves a heterogeneous integration with high integration density,data rate,and bandwidth and a short interconnection distance.The TSV technology in 3D integration can provide a high-speed signal interconnection in the packaging system with the best signal transmission path,which is of great value in realizing high-performance computing and applications in the Internet of Things with high speed and capacity.Therefore,in relation to the TSV integration system,studying the key technologies of electrical signal transmission,including the electrical model and characteristics of the transmission structure,and the system transmission scheme is of great significance.This research mainly aims to analyze the high-speed electrical signal transmission path and the transmission scheme design in a TSV based 3D integration system.The details are as follows:1.Aiming at the core structure of the information transmission path in the TSV integration system,this research conducts TSV structure evaluation,electrical modeling,and performance analysis.A new bar TSV(B-TSV)structure is proposed in accordance with actual applications.The transmission characteristics of the B-TSV structure are analyzed through 3D finite element and equivalent circuit modeling.This structure is compared with a traditional cylindrical TSV structure.The results show that the B-TSV structure has good electrical characteristics,which can lower the area of TSV on the chip while keeping the transmission performance unchanged,owing to the strong noise abatement capability.2.An optimization design method based on segmented transmission line(STL)is proposed for the horizontal redistribution layer(RDL)of the information transmission path in the TSV integrated system.From the analysis of the discontinuous and imperfect characteristics in the information transmission path,a segmented transmission line is used to design RDL in segments.In combination with the TSV equivalent electrical effect,a genetic algorithm is adopted to optimize the segmented parameters and achieve the best transmission performance of the information transmission path.3.As required for suppressing common-mode noise in high-speed signal transmission in the TSV integration system,a common-mode noise rejection filter(CMF)is designed and implemented.In particular,a CMF with a reflection-type lumped cell is designed on the basis of the prototype of a low-pass filter with single-ended signal transmission.The circuit component parameters of the common-mode noise filter are designed,and the physical design and performance evaluation of the filter are completed through full-wave electromagnetic simulation.The layout design of the filter sample for testing is carried out,and the sample processing is realized via a semiconductor process manufacturing technology.On the basis of the test of sample performance,the main parameters of the TSV-based common-mode noise rejection filter include a differential mode cutoff frequency of 16.8 GHz,a common-mode rejection stop band of 5.3-16.0 GHz,and a proportional bandwidth of 100%.The filter has good performance,which verifies the feasibility of the design method.4.In accordance with the requirements of high-speed large-bandwidth information transmission in the integration system,a high-speed and large-capacity information transmission scheme is studied.A highly reliable information transmission scheme is formed by adopting TSV array parallel transmission and introducing a channel error correction coding technology.The TSV array is mapped to the code word to improve the anti-interference/noise capability of the transmission path and realize high-efficiency transmission of high-speed and large-capacity information at a low bit error rate.