.10-bit 80mhz Adc Key Unit Of Pipeline Architecture Design

It's introduced in this paper a 80MHz, 10bit, 3.3v pipeline architecture CMOS A/D converter. Important blocks such as the Sample and Hold Circuit are analyzed in detail.The chip is designed using SMIC 0.35um 2P4M mixed-signal CMOS process.Considering the speed, power dissipation and dynamic specification, the 3-stage, 3.5bit/stage structure is introduced. A digital calibration circuit eliminates errors between stages. Cascode Op Amps provide the Switch Circuit high speed and good precision. The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.The ADC circuit have been simulated with HSPICE simulator in the Cadence design environment. SFDR is 70.6 dB when Nyquist sampleing sinusoid input signal. The chip's total die size is 4.5 * 2.4 mm2 and has 28 pins in SOP package.This chip applies to video management and digital operation.