Speed ​​frame Synchronization Formatter

High-speed data transfer technique is one of the key hotspot aspects in modern communication system. It becomes more difficult to realize frame synchronization with higher data transfer speed, and this field applies mostly high-speed digital circuits technique. So this dissertation named "High-Speed Frame-Synchronizer" tries to resolve the application of high-speed digital circuit technique in satellite communication. High-Speed Frame-Synchronizer is an absolutely necessarily key device of the Remote Sensing Satellite's Ground-Receiving system. It is mainly used to format the high-speed data stream, so that computer can get the beginning address of every frame of the high-speed data stream, and then data stream would be send to computer for pretreatment through high-speed interface. The observing ground satellites of modem time have higher resolving power, so that they require ground station system with more performance accordingly. As the key device of ground station system, High-Speed Frame-Synchronizer needs to have higher performance also. High-Speed Frame-Synchronizer not only is required higher speed but also requires to be used for more kind of satellites. It is impossible to buy the High-Speed Frame-Synchronizer overseas because of high price, and more important, the way of data format and encrypt of military satellites is involved the secret of nation. We must research and produce the key device by ourselves. The achievement in the technique will help our country in constructing the system of new Remote Sensing Satellites and military satellite's ground stations. The dissertation accomplishes the design, simulation and realization in software and hardware of High-Speed Frame-Synchronizer, which its highest speed is 150Mbps. The High-Speed Frame-Synchronizer can be used to work for many kind of satellites, and can be controlledby computer initializing. The High-Speed Frame-Synchronizer can be controlled by changing parameter as followings: IQ routes information, the length of frame head, the content of frame-synchronization codes, frame-synchronization error sufferance, frame protect sufferance, frame protect coefficient, the length of frame. To achieve design target, the author referred a great deal of correlated data, and accomplished hereinafter parts: compile programs of FPGA to realize main design, simulate system, protract high-speed PCB board, compile single chip machine's programs for control, and debug experiment.The results of experiment indicates that the High-Speed Frame-Synchronizer's design meet the request of high-speed and flexible control.