Lsi Design Method Of Automatic Placement And Routing

With the high-tech changing quickly, VLSI place and route has been applied into many fields, such as computer, semiconductor, communication, space flight and aviation, etc. This technology is protected as an important secret by famous plants of the world. In my country, there are few companies holding the technology and spacious market foreground. At the same time, IC design units who have no standard cell library must face two chooses: one is to design a library according to foundry's technology independence, and another is to find feat associates having library. This paper mainly introduces how to place and route associating with SE, Ambit, Pearl, Verilog_XL and convert Verilog and VHDL codes into layout. All of the hard IP reusing can be concentrated into a single environment, including building library, editing layout, placing and routing, DRC and LVS. Thus designers must not change their working interface when reusing hard IP.VLSI place and route hold performance and design as follows:It can give a tight link between logic and physical design, fully timing -driven routing, single-pass optimization. Mixed-level, timing-driven floor plan provides predictability, quick iterations and control for physical design. A front-to-back, timing-driven ASIC design solution supports process-wide timing constrains for design accuracy and control. At the same time, by combining floor planning and placement, designers can distribute components evenly across the array while retaining clusters of highly connected components. Other features include full over-the-cell obstruction-based routing, while support for rectilinear block alleviates artificial constrains on block design, increasing design flexibility and layout density. Parametric macros are allowed to represent arrays (such as RAM) and parameterized logic functions in a dense, easy to use and flexible form.All above have been proved by digital audio, 80C51 and the perpetual calendar designs separately.