The Design, Based On The 386ex Cpu Real-time Edac

Zhou Shengyu(Computer Application)Directed by Chen XiaominBecause of the radiation in space enviroment, the data in SRAM of the aerospace computer will nomally experience Single Event Upset (SEU) errors at a scale of small probability. Had not been corrected in time ,these errors would effect not only the performance of the computer system but also the transmission of the key data.. A method about how to design a real-time EDAC circuit based on aerospace computer which cantains 386EX CPUis is described in this paper.The main subject of this paper concentrates on the design of the EDAC (Error Dectection and Correction) circuit which can accomplish the function that correct the errors of the data in SRAM.Above all, [12:8] Harming error correction theory is mentioned in this paper.The EDAC circuit designed by VHDL can works normally at different frequency of the CPU clock such as 66MHz\50MHz\40MHz\33MHz. The EDAC function of the circuit can also be disabled by software tool.Meanwhile,some basic devices such as AND logic,OR logic,NOT logic and some small scale integrated circuits are also integrated in the FPGA.The designing process of the EDAC circuit is described in the paper. The time simulation is analysed, too. The designment of the circuit has access the hardware debug, and can woks normally.