Research On Hardened Design For Memories Against Seu Based On Error Correction Codes

There are many kinds of high energy radiation particles in radiation environment such as space or ground radiation environment.Electronic devices used in the radiation environment will be hit by radiation particles and then be affected by radiation effects.As for widely used memories,if a single radiati on particle hits through the sensitive cell,the logical stage of the cell will be upset,which is named Single Event Upset(SEU).SEU will produce a soft error in memory stored data and then result in some reliability problems in system.Therefore,SEU hardened design is necessary during the reliability design for memories used in radiation environment.As the technology size of integrated circuits scales down to nanometric field,an SEU can result in the upsets in several cells,which is named Mutiple Cell Upsets(MCUs).This phenomenon is becoming more and more serious as the technology size shrinks down,and has been one of the challenges in hardened memory design against SEU.Among many kinds of hardened techniques for memories against SEU,Error Correction Codes(ECCs)used in system level is one option to efficiently deal with soft errors caused by SEU and provides a high level of reliability at low cost of redundancy.Designing different ECCs used in different applications has become the focus of research in this field.This dissertation focuses on the hardened design for memories against SEU based on ECCs.According to different radiation environments and different application requirements,how to efficiently deal with SEU at low cost of redundancy has been researched and presented.The main contents of this dissertation are organized as following.(1)Reseach on the hardened method of low redundancy matrix-based codes.A matrix-based codes construction method which provides a flexible adjacent errors correction capability and costs a low hardware overhead is presented.Firstly,the data is placed into a two-dimensional matrix format.The horizontal error detection codes and Hamming codes are added into every row of the data matrix and the vertical error detection codes are added into every column to form a matrix code.Secondly,high adjacent errors correction capability is designed using the proposed optimization data matrix placement.Depending on the proposed pairty bits sharing and the corresponding decoding algorithm,the goal of low redundancy is reached by reducing the number of parity bits.The relationship of the size of matrix,the number of parity bits,and the correction capability is presented.Finally,the function and reliability of the proposed low redundancy matrix-based codes are verified and analyzed.The results show that the proposed codes can provide a high SEU hardened capability for memories at low cost of hardware overhead.Through adjusting the dimension of the data matrix,different levels of error correction capability can be achieved using different numbers of parity bits.This advantage can provide more choices for chip designers.(2)Research on the hardened method of low redundancy Orthogonal Latin square(OLS)codes.A method to construct the extended OLS codes to directly protect typical memory data is proposed.It can correct several random errors to protect memories.Firstly,the construction rules for OLS parity check matrix and one-step majority logic(OS-ML)decoding algorithm is studied.Based on that,a construction method applying the extended OLS codes used to protect typical memory data is proposed,and the codes are OS-ML decodable.Secondly,an SEU hardened memory using the proposed OLS codes is implemented and the circuit performance is evaluated.Compared to the existing shortened OLS codes,the results show that the proposed method can maintain the random errors correcti on capability with fewer parity bits and thus requires a lower hardware overhead.Then,based on optimization of the parity check matrix and minor modification on the decoding algorithm,a method of constructing DEC-TAEC(Double Error Correction-Triple Adjacent Error Correction)low redundancy OLS codes is presented to extend the correction capability of OLS codes,which can correct double random and triple adjacent errors.Finally,the function of DEC-TAEC OLS codes is verified and the decoder is implemented.Compared to the existing similar techniques,the evaluation results for the decoder circuits show that the proposed DEC-TAEC low redundancy OLS decoder has an advantage in terms of circuit area,delay,and power consumption,which is more suitable in high-speed SEU hardened memories application.(3)Research on the optimization for error detection capability of the SEC-DED(Single Error Correction-Double Error Detection)codes.SEC-DED codes,which belong to Hamming-based codes,can correct one error and detect two random errors.Their error correction capability is related to the elements in the parity check matrix and is directly proportional to the number of parity bits.SEC-DED codes have an advantage of error detection capability as they can determine if there is a double error by simply judging the parity of the weight of the syndrome.in this dissertation,the construction of SEC-DED parity check matrix and the error detection and correction algorithm are firstly researched.Secondly,a couple of constrains which can extend the error detection capability of SEC-DED codes to three adjacent errors are presented,and a method of obtaining SEC-DEDTAED(Single Error Correction-Double Error Detection-Triple Adjacent Error Detection)codes is proposed.A searching algorithm is used to obtain the best parity check matrixes.Then,the method is implemented and the circuit performance is analyzed.Compared to the existing similar techniques,the results show that the proposed codes require no more additional parity bits and cost lower circuit overhead and shorter decoding delay.It is more suitable for the memory applications in which errors detection can trigger the exception handler part to deal with the fault.Finally,a fault secure hardened scheme has been proposed for memories protected by error detection codes.This scheme can be implemented in software level and does not need to modify the decoder circuit.The correctness of the critical bit can be detected when there are errors detected by ECCs.If the critical bit is not affected by errors,the corresponding circuits can continue to work.This method can avoid the case,in which the exception handler part is triggered by the error detection signal of ECCs time and time again.Thus,the time can be reduced,and the efficiency of system operations can be improved.