Test Design Of StrongARM Microprocessor

The IC design, manufacturing and test are three vital phases of the integrated circuit industry chain. As the size of the transistors getting smaller and smaller and the integration degree increase continuously, it is difficult to test a chip make use of traditional methods. So it is necessary for us to design test architecture when we designing a chip, which calls DFT.StrongARM microprocessor is an embedded microprocessor which is compatible to the ARM family microprocessor. On the basis of the architecture of StrongARM, we studied scan path, boundary scan and BIST architectures. We finished designing BIST controller of the embedded memory and JTAG controller of StrongARM.The main idea in scan design is to obtain observability and controllability for flip-flops. This is done by adding a test mode to the circuit so that when the circuit is in this mode, all flip-flops functionally form one or more shift registers. In this paper, full scan methodology and multiplexer based flip-flops are used inside the chip.BIST architecture means the stimulus generators and the response verifiers are embedded within the circuit. On the basis of the architecture of the SRAM in StrongARM, we designed a BIST controller using March arithmetic. It uses external instructions to control the transform of the FSM, and achieve many test algorithms by assembling the test elements. By this way, the memory BIST controller is more flexible, and can achieve less area overhead.IEEE JTAG 1149.1 boundary scan standard gives us a standard mechanism for very different segments of the electronics industry to support testing. According to IEEE 1149.1 standard, we finished designing the boundary scan controller. Additional instructions are added to the controller, including internal scan instruction and BIST start construction. Then, the internal scan, memory BIST and boundary scan are all controlled by the boundary scan controller. By this way, many external ports can be saved.