Asic-based Back-end Design Of The Radar Signal Processing Chip

With development of Integrate Circuit design methodology, the design level of ASIC chip has been improved greately, and ASIC design enters a new epoch based on VDSM: system on chip (SoC). However, the use of VDSM technology, and the characters of system chip such as large scale, complexity and high frequency, make traditional design method incapable. Flatten layout leads to insufficient of process capability and huge time consumption. Therefore, hierarchical layout design is developed to meet the need.This dissertation introduced the ASIC backend design flow based on hierarchical design method. In the thesis, we make a deep research on the key technology in ASIC backend design, such as Floorplan, Power-supply distributed design, Clock Tree Synthesis, NanoRouting, Layout Verification. Based on these key technologies, accompanied with SMIC 0.13μm technique and utilize of APR tool—SoCEncounter of Cadence, we accomplished the backend work of a Radar chip which scale is about 5 million gates. The main works can be summarized as follows: Floorplan, Power-supply distributed design, Silicon Virtual Prototype design, Partition, Block Implementation, Top_level Implementation, Chip Assembly, Layout verification.