Study And Realization Of Submicron Logic Integrated Circuit Testing And Verification

With the rapid development of integrated circuit technology, the process geometries of Application Specific Integrated Circuit are shrinking and the density of ASIC increases greatly. So the test and verification plays a more and more important role in ASIC design. The test and verification always consumes about 70% of the design effort. The number of test and verification engineers is usually twice the number of RTL designer. After the project finished, the code for test makes up to 80% of the total code volume. Verification is used for check whether function and timing match the design specification, and test is used for check whether there are manufacture errors in chips. The changing role of test has led to the need to break down the traditional barriers with design and fabrication, and is leading to a fusion of these activities, such as Design for Testability which can test timing circuits in chip, Built-in Self-test which could test RAM in chips, software/hardware co-simulation which could test functions, etc.. How to improve the quality of test and the coverage rate of verification and shorten test period has been the essential obstacle for test process. Based on above issues this paper studies in-depth on design for test and verification of sub-micron digital IC design, and the proposed design method was applied in Gas Volume Chip (GVC), whose process is 0.35um 1P4M CMOS.The paper introduces the function and technical specification of the GVC chip, including background, functions and technology parameter, etc. The paper elaborated the theory and approach of Design for Test, including design flows of full scan, memory Built-in Self-Test (MBIST), Boundary Scan Test(BSD). With ensuring the observable and controllable coverage of the system, DFT could improve the fault coverage and reduce test time. For full scan, the paper analyze the fault models and solute the violations. For MBIST, it introduces the specific design scheme around RAM. For BSD, it introduces the specific design flow by EDA tools. Furthermore, full scan and MBIST are implemented in GVC. Lastly, the paper analyzes the theory and approach of verification, including simulation-based verification and FPGA prototype emulation. For Simulation-based verification, designer creates testbeches and finished system level and behavioral level simulation in GVC. FPGA prototype emulation is implemented in the FPGA chip CycloneⅡEP2C20 from Altera Inc.. At last, the chip pass the test and verification. It is sent to be taped out and then brought into production.