Study On ASIC Logic Verification Technology Based On FPGAs

As the ASIC design size growing larger everyday, ASIC verification is today's most challenging issue for ASIC designers. Traditional verification approach, such as software simulation and hardware emulation, can hardly meet the emerging requirement. A new ASIC verification approach based on FPGAs can shorten development cycle efficiently and implement verification more quickly and completely and satisfy the requirement of ASIC verification better. FPGAs have been playing an important role in ASIC design cycle, but due to very large size of today's ASIC designs compared to FPGAs, it is impossible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the large design into multiple small size modules and fitting those modules into multiple FPGAs.This paper has deeply studied reconfigurable interconnection structure of prototype system and logic partitioning algorithm. We studied and analyzed two typical interconnection architectures and present a new asymmetry interconnection architecture. Compared with symmetry interconnection architecture, this architecture can provide more flexible interconnection traces and I/Os, and support more I/O standards.On software, we studied two sorts of today's logic partitioning algorithm, and then presented a new partitioning algorithm based on the module of design code. This algorithm has three important characters: 1) it is based on the design code, 2) it makes module as minimal partition cell. 3) It analyzes the resource of each module used and applies the information to partition the design into a number of FPGAs. Because of the potential parallelism in the process of logic partition, we also studied parallel logic partitioning algorithm. In this paper, we present two parallel logic partitioning algorithms based on different strategy of task allocation and give corresponding implementation.At last, we made an experiment of ASIC logic partition and verification using new asymmetry interconnection architecture. The result shows that, it can get higher performance of ASIC partitioning with new architecture. It can improve the utilization of interconnection trace and provide more flexibility for partition algorithm and satisfy the requirement of large ASIC verification better.