Soft Error Method Of Deep-submicron Fpga Interconnect Anti Studies

Because of the excellent field programmable flexibility and universality, FPGA is widely used in defense equipment, civilian communications, consumer electronics, automotive, medical and other fields. However, with the continuous technology scaling, the reduction of nodal capacitances and lowering supply voltage have severely impacted the soft error rate of integrated circuits. The high-energy charged particle striking at the sensitive nodes could induce soft error in user design by changing the configuration bits of an SRAM-based FPGA. Since there are a large fraction of the programmable bits are used to configure the interconnection inside FPGA, without an effective SEU-mitigation method, the interconnects of SRAM-based FPGAs is prone to soft error. Statistic number shows that, the SEU-induced soft error in the interconnects accounts for 80% of the total SEU-induced soft error in an FPGA.FPGA development consists of the hardware design and supporting CAD development environment design. This thesis improves the interconnects soft error immunity of SRAM-based FPGA in two ways, SRAM cell structure and the routing module of the CAD flow in the development environment.To improve the soft error tolerance of SRAM cells would be one of the most efficient methods to enhance the reliability of the SRAM-based FPGA, since SRAM cells store the configuration of design. In this thesis, one new SRAM cell design, 8T-SRAM, is proposed, which mainly aims at reducing the soft error rate in FPGA. This thesis verify the read/write speed, leakage power and the soft error tolerance of 6T-SRAM, ASRAMO and 8T-SRAM using SPICE simulation with the industrial 65 nm CMOS technology. Simulation result shows that the proposed SRAM design can achieve better soft error immunity. The soft error rate of 8T-SRAM is 44.20% less than that of conventional 6T-SRAM.At the same time, this thesis investigates the routing module of the FPGA CAD flow in the development environment and the interconnect error type induced by SEU. According to the investigation, an SEU-mitigation routing algorithm, SD-Route, is proposed based on the classic routability-driven routing algorithm in VPR. The SD-Route is implemented in the FDE2010 flow developed by Fudan University, and fault injection tests are carried on the FPGA device, FDP3, which is also independently researched and developed by Fudan University. The experimental result shows that, the soft error rate of the design of SD-Route SEU-mitigation routing flow are 20.02% less than that of the classic routability-driven routing flow.