Design And Implementation Of High Definition IPCamera Monitoring System

Profitted from the rapid development of network technology the network video monitoring system has been growing fast in recent years.In this research the author focused on the realization of an HD video monitoring network system on FPGA.The author realized video image acquisition and video image compression coding system.The author used CCD as the front data-capturing component and preprocessed image data from CCD by circuits described with VHDL language.The preprocessed image data was compressed and coded on FPGA in order to realize the compression of static JPEG images.In this paper the design of video image acquisition system was detailed.The video image acquisition system included signal-processing board,signal-splicing module of four channels, DDR3 arbitration controller, color conversion module and image flip module.The DDR3 arbitration controller was the most innovative breakthrough in this paper.Then the video compression coding system was introduced in detail.The principle and significance of the compression system was introduced. The design of JPEG static image compression coding on FPGA was then described.In this design,a static picture was fist managed by two-dimension DCT transform,then quantified,then AC coefficients and DC coefficients separated,then arranged in Zigzag way,then entropy coded.The managed picture data was then coded in JPEG format and transmitted to PC by RS232 serial port.Tb.en the picture data was transformed to JPG file on PC by the software TTHexedit.The final test shew that this project has achieved the desired goal. The image capture system in the front part and the compressiom system in back part were both realized.