Design Of New Calibration Circuit Of 16 Bit SAR A/D Converter Of Medium High Accuracy

Compared with other types of ADC,the successive approximation register analog to digital converter(SAR ADC)has main advantages of simple structure,low power consumption,high resolution,small size and so on.The SAR ADC plays a very important role in the medium resolution market.Therefore,it has been widely used in precision instruments,industrial data acquisition,medical and aerospace fields and so on.According to the needs of industrial,medical and military applications,higher accuracy and speed of SAR ADC are required.Because of the limitations of fabrication precision,calibration techniques are needed for the accuracy of SARADC,when the resolution of SAR ADC is higher than 12bit.This paper is aimed at the research on the structure of calibration circuit of a 16 bit SAR ADC for a military project.Firstly,the system structure,parameters and the non-ideal factors which affecting the accuracy of SAR ADC are mainly studied in this paper.A calibration method is adopted.The calibration method is mainly divided into three processes which are used for obtaining the error codes,calculating the calibration codes and compensating the calibration voltage.Then,a calibration capacitance array which matches with the calibration method is designed.Meanwhile,the range and accuracy of the calibrated capacitance array are adjustable.By adjusting the value of coupling capacitance and balance capacitance reasonably,the calibrated capacitance array can produce a step voltage of 19.1563?V and the full output voltage of 4.904mV.Based on the deep analysis of the operation principle of SAR ADC,the relationship between the error voltage and the calibration voltage is deduced in detail.Finally,the calibration method is verified.Verilog Hardware Description Language is used to perform the functional simulation of the calibration method.It is found through simulation that at least 32 clock cycles are needed in the.transformation phase to complete the conversion of one bit of data.Therefore,a parallel structure with multiple DAC calibrations is proposed to improve the calibration efficiency.Moreover,the whole calibration capacitance array is simulated and analyzed based on the SMIC 0.18?m PDK(process design kit).It is indicated through the simulation results that when the width length ratio of complementary CMOS switch transistor is 2:1,the voltage needs about 1.3ns to transfer.When the width length ratio is 10:1,the voltage needs about 370ps to transfer.In order to keep the voltage establish time of all capacitors consistent,it is necessary to trade-off between the switch speed and the layout area.