Research And Design Of Full Digital Frequency Synthesizer

As the rapid evolution of wireless communication systems, they have changed our lifestyles. It’s also believed that, as the development of technologies, they will bring much more significant influences to us. As the local oscillation signal generator in wireless communication systems, frequency synthesizers are of great importance. Normally wireless systems will impose strict requirements on local oscillation signals, consequently RF frequency synthesizers are constantly a hot research topic.As the development of CMOS technologies and scaling down of the devices, conventional analog circuits design is facing more and more obstacles and challenges, such as low supply voltage, device mismatch, leakage and so on. However, digital circuits are immune to these problems, and on the contrary, they could work at faster speed with lower power consumption under advanced technologies. As a result, digitally implementation of conventional analog circuits, such as frequency synthesizers, has drawn more and more research efforts.In this thesis, the research and design progress of an all-digital frequency synthesizer is presented. The first part is about the system design, analysis and modeling. For frequency synthesizers in wireless communication systems, the output phase noise is of great significance, and the simulation of phase noise is also very important. In order to accomplish the phase noise simulation, both frequency-domain and time-domain model are illustrated. In the next part, analysis and design of the building blocks in the system are introduced. There are two typical problems that need to be solved in the design of all-digital frequency synthesizers. The first one is the integer-N artifact, which means the possible in-band phase noise deterioration that may happen when the frequency of the output signal is exactly an integer multiple of the reference clock. In order to solve this problem, a spurious-free time-to-digital conversion is realized by utilizing a special time-to-digital converter structure. The other problem is the meta-stability problem, which denotes the possible impacts in the phase detection block brought by the meta-stability phenomenon of CMOS devices. To tackle this problem, a meta-stability free phase detection architecture is proposed. Finally, the circuit was implemented with TSMC65nm CMOS technology with a core area of0.385mm2. An output range of8.95-11GHz is realized, which is20%compared to the central frequency of10GHz. With a reference clock of50MHz and a frequency control word of200, the measured phase noise from a10GHz output is-89.4dBc/Hz at100KHz offset and-106.4dBc/Hz at1MHz offset. The system bandwidth is about500KHz and the locking time is about8.5us according to the measurement. The whole system consumes15.74mW from a supply of1V.