The Solution Of Dual Graphics Technology In Back - End Design

As the VLSI technology scales into20nm, half pitch of this technology node is32nm, the most advanced immersion scanner can only support maximum half pitch40nm thus does not have sufficient imaging capability. Extreme ultraviolet (EUV) technology at wavelength of13.5is considered a practical light source for next-generation lithographic technology. However, before EUV lithography is suited to mass production, an appropriate exposure technology is needed to fill the gap between immersion ArF and EUV scanners. Double patterning technology (DPT) is a technology that extends the usability of immersion ArF system. Notably, DPT relaxes the minimum pitch of a circuit layout for each split exposure; thus, ArF water-based immersion systems can be extended to20nm technology node and beyond. DPT is a promising technique that bridges the anticipated technology gap for next nodes by utilizing current tools without changing much. This paper elaborate idea solution using EDA tools to handle DPT, that is DPT-aware throughout place and route, followed by a quick and independent compliance checking, so any problems can be found early in the design cycle. Another key aspects of physical design on which DPT has a significant effect is extraction. These effects have to be modeled properly to ensure accuracy signoff timing. Synopsys IC Compiler automatically honors the requirements of double patterning during place and route by employing techniques to avoid double patterning violations by obeying the double patterning design rules specified by the semiconductor foundry. Starting from placement, double patterning spacing is used to prevent double patterning violations due to standard cell abutment. The router identifies congestion spots by considering additional double patterning routing resources. The map of congestion hotspots can be used to adjust the floorplan or by the IC Compiler placer to carry out congestion removal as early as possible. Lastly, router prevents, detects and fixes double patterning routing violations. User can check the layout with signoff-quality DRC by using In-Design physical verification with IC Validator to accelerate design rule convergence with IC Compiler. The new In-Design technology enables IC Compiler and IC Validator to work closely to provide a highly productive solution for 20nm designs. Physical Verification for DPT solution includes library cell coloring, DPT compliance check and automatic repair technology. The Compliance check ensures the layout is decomposable for two alternating patterns. StarRC, the industry leading edge extraction tool has also been enhanced to model the effects of DPT to provide accurate models so signoff result matches closely with silicon.