Improved Integrated Circuit Manufacturing Process To Extend The Method Of Some Kind Of Dram Refresh Cycle

The refresh time of DRAM IC chip will directly affect on the power consumption and performance of this memory. More longer refresh time is prefer to degrade the power consumption of DRAM IC chip within certain condition.This paper study upon one certain DRAM chip about its manufacturing process and process integration technique to prolong the refresh time. There are lots of methods to prolong the refresh time, some one pay more attention on the material species, some one pay more attention on the circuit structure design. This paper will emphasis on the process and process integration technique which will be used in the DRAM manufacturing.We did series experiments on two mainly aspects. One is add the charge storage, the other is reduce charge loss. As to these two aspects, we take several new process and process integration method such as DSTI CMP, CLD implant, HSG doping & RTO, etc. The basic theory method for us to discuss is that so called "suppose—experiment—validation", by this method, we start our research about this project.In the experiment, we found that add the Stack Capacitor can level up the capacitance seriously, and also we found that the capacitance would increase if we take a good control about the P dosage after HSG formation and continuously use RTO to active the implanted ion. The refresh time prolonged much when the capacitances increase.In the experiment, we also found that CLD implant can effectively decrease charge loss in channel, and this can prolong the refresh time.On the other hand, reduce the cell source/drain electric field also can decrease charge loss and prolong the refresh time.Wish this paper be helpful to those ones who interested in DRAM research.