A Used In The Adaptive Dynamics Of The Gain Unit Embedded Dynamic Random Access Memory Refresh, And The Write Voltage Adjustment Programs

2T PMOS gain cell, one of new capacitor-less embedded DRAM cells, is used as the core cell of the presented low refresh power eDRAM chip. In this paper, the advantages of gain cell such as small cell size, logic process compatibility and etc are discussed. Furthermore, four design difficulties, small data retention time, negative voltage requirement, temperature and disturbance sensibility of data retention time are performed detailedly. Focusing these four difficulties, research and design work have been done to improve the cell's characteristics. With the improvement of process and layout, data retention time gain an increase by 4 times. Negative voltage transmission circuit and on-chip negative voltage charge pump are implemented to meet negative voltage requirement. A new adaptive dynamic refresh and write voltage adjustment scheme based on monitor cells is proposed to resolve the sensibility of data retention time. By using the scheme, an average 25%～30% refresh power reduction is gained at work mode and 50% reduction at standby mode.