Study On Radiation Hardened Embedded Memory Based On Gain Cells

In space environment, particles with high energy strike into semiconductor materials. A large amount of electron-hole pairs are generated and cause radiation effects. Electronic systems face threats of radiation effects.The main effects are total ionizong dose effect and single event effect. Single Event effect causes wrong data in the electronic systems and leads to fatal functional errors in the space craft. In the electronic system of the space craft, embedded memories which take most of the chip area are affected by the single event effects strongly and are the weakest device in the system.Currently, the hardened embedded memoris based on SRAM generally lead to a large increase at the area, and they increase the area and cost of the electronic systems on the space craft. Secondly, the stability of the 6T SRAM cell decreases quickly as the ratioed operation of the 6T SRAM cell. There are disadvantages in the radiation hardened embedded memories based on SRAM. The radiation hardened embedded memory based on gain cells is studied and the contributions of this paper are shown below.Firstly, a high density and TID/SEL hardened 4P eDRAM cell is proposed based on the study of gain cells. Based on the characteristics of the 4P eDRAM cell, High-Vt PMOS write access transistors, negative word line technology, diffential structure and voltage boosting technology are used to improve the operation characteristics and data retention time. The 4P eDRAM cell is logic compatible, have good performance with small area.Secondly, DMR technology and column direction bit-interleaving (CDBI) technology are proposed to harden the 4P eDRAM cell from SEU and MCU. Based on the SEU effect of the 4P eDRAM cell, DMR technology is proposed to harden the 4P eDRAM cell from SEU. Based on the MCU effect of the DMR harden cell eDRAM (HGC eDRAM) cell, the two basic 4P eDRAM cells are separated physically by CDBI technology to realize hardeness of MCU. Simulation results demonstrate that the HGC eDRAM cell implements good hardening performance from SEU and MCU. The HGC eDRAM cell is compared with the radiation hardened designes based on 6T SRAM, and the result show the HGC eDRAM cell implements good hardening performance and has a small cell area.Thirdly, an adaptive refresh period (ARP) control system is proposed to reduce the refresh power of the HGC eDRAM. The static power and refresh power of the HGC eDRAM are studied. Based on the effect of temperature and access statistics on the retention time of the HGC eDRAM cells, the ARP control system based on Replica technology is proposed. The ARP controls system refresh the HGC eDRAM Bank at a high frequency at high temperature and at a low frequency at low temperature, the refresh power of the HGC eDRAM is reduced. At low temperature, compared with the tradiaitonal fixed period refresh method, ARP control system reduces the refresh power by 99.72%. And the ARP control system implements low detection error and low detection power.Finally, a stage-interleaving hidden refresh method is proposed for the HGC eDRAM. In traditional DRAM designs, external accesses are offen delayed by internal refresh operations, the access speed and the bandwidth avalibity is reduced. To solve this problem, the stage-interleaving hidden refresh method is proposed. The hidden refresh avoids the conflict between the external accesses and internal refreshes. The external accesses are performed immediately without any deley. The access delay is redueced and the bandwidth availability is increased to 100%. A dual-Port HGC eDRAM is proposed and the bandwidth is increased by 100%. A fast hidden refresh method is proposed based on the stage-interleaving refresh method. The clock cycles needed to refresh the whole bank is reduced by about 50%. The effectiveless of the hidden refresh is verifided by a HGC eDRAM bank with the hidden refresh method.