High Speed Dynamic Random Access Memory Programmable Embedded Built-in Self Test Design And Optimization

In recent system on chip (SoC), embedded memory is becoming dominant instead of logic. And with the rapid development of portable electronic devices, embedded Dram which is a branch of embedded memory is used more and more widely because of its high storage density and low power consumption. In this situation, the yield of the whole chip is decided by the memory’s more and more dramatically so the test for embedded memory is important particularly.A new kind of high-speed embedded Dram with2T gain cell acting as its storage cell is introduced in this paper. Its advantages are high storage density, high access speed, nondestructive operation and compatibility with standard logic technology.The advantage of this memory brings challenge for chip test. How to save test time and guarantee high fault coverage during high-speed test are big problems. In this paper, a programmable built-in self-test (PBIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM. This PBIST implementation consists of instruction set architecture (ISA) and hardware. A4-stage instruction pipeline for instruction execution makes at-speed test possible. Various kinds of test algorithms, including March, Galpat and Hammer test, can be performed by executing different instruction combinations. A16KB Gain Cell memory with the PBIST is fabricated in SMIC’s0.13μm CMOS technology. Silicon measurement shows that the PBIST can perform at-speed test at high clock frequency of200MHZ by various algorithms mentioned above.As some problems on cell yield are found in the chip mentioned above, an optimized PBIST scheme is also presented. This PBIST can optimize the operation timing sequence and measure the data retention time of Dram. Silicon measurement shows that the introduction of this PBIST can improve the cell yield and get the data retention time of the storage cell.The PBIST scheme aiming at a new kind of high-speed embedded Dram based on2T gain cell presented in this paper and its optimization can guarantee high fault coverage, improve test speed, reduce performance request for ATE, reduce the pin overhead and optimize the memory under test automatically. The work of this paper is good research and exploration for embedded memory test technique.