Embedded Gain Unit Memory For Data Access Rate And Resistance To Soft Errors Ability To Design Research

With ever-increasing development of handheld mobile devices, people put for-ward further demands for high performance embedded DRAM in SOC. They need to not only keep the inherent advantages of high bit density and low power consumption, but also compare favourably with SRAM in terms of speed and logic process com-patibility. Meanwhile, the issues of how to improve retention time, data availability and soft error rate are also urgently to be solved.Nowadays, as one of the most potential candidates for the next generation of em-bedded memories, capacitor-less DRAM has been a hot research field in novel mem-ory designs. This is mainly due to its outstanding performance merits. In particular, a number of international and domestic academic institutions and companies put a lot of effort into researching gain cell memory that enough to explain its importance.By optimizing the layout of traditional gain cell, the cell size is typically 60% smaller than that of an SRAM cell with the same technology. Some novel structure and process tricks are adopted in order to increase storage node capacitor and to sup-press cell leakage that improves retention time 20X. In addition, based on independent read/write path and characteristics of gain cells, the stagger hidden refresh scheme can achieve 100% data availability without significant peripheral overburden. Besides above techniques, a row-based ECC architecture is developed to deal with the prob-lem of high soft error rate when cells are scaled to more advanced technology.In this paper, A 64 Kb embedded DRAM test macro of 2T gain cell is demon-strated including system function, array organization and peripheral circuits design. Three novel concepts are proposed and verified for the first time with 1.35mm x 1.35mm chip size on SMIC 0.13μm logic process.