Design Of Dram Refresh Clock Generation Circuit Based On Temperature

With the rapidly development of integrated circuits and microelectronic technology, high-performance processors for embedded memory system put forward higher requirements, high memory density, low power, high speed, low cost is the future direction of development of memory, how increased integration of memory, reducing the refresh power consumption is still the research focus.In this thesis, the above problems is proposed based on the temperature of the memory of a true sense of the adaptive refresh program. Aiming insufficient conventional memory refresh circuit design has pointed out the need for temperature adaptive refresh circuit.2T memory cell core with an object, for temperature increases, the leakage current increases, the information retention time shortened features, combined with existing features based on the temperature sensor refresh, take into account all area, power, technology and other performance between bound tightly around the relationship between the "temperature Voltage refresh frequency " the proposed redundancy associated with the temperature of the unit is joined as a PTAT temperature sensor monitoring unit studied in the storage array has good linearity, small footprint compatible with MOS technology, real-time temperature monitoring sensor circuit.In the source oscillation frequency varies with temperature having to request detailed analysis of the frequency of the VCO to change the ring method, and select the type of current starvation ring voltage controlled oscillator circuit, the output voltage of the temperature detection sensor to the circuit as the control voltage, is designed based on the temperature of the DRAM refresh clock generation circuit.The thesis is based on the standard AMI0.6um CMOS process, the simulation results show that the oscillator circuit design meet the DRAM refresh requirements.