A With Adaptive Frequency Calibration Of Fractional Frequency Synthesizer Design

The purpose of this thesis is to research and design a fractional-N frequency synthesizer for the Audio Codec applications, the typical output frequency is 12.288MHz.This thesis mainly researches and discusses the design of PLL system and Delta-Sigma modulator; a fractional-N frequency synthesizer with 2-order digital Delta-Sigma modulator is implemented.From the system point of view, firstly, based on the method of maximum phase margin optimization, the thesis makes a modeling and analysis of a 3-order charge pump PLL system, and summarizes the non-ideal factors for circuit design; then, this thesis summarizes the design method of digital△Σmodulator, and gives a reducing spurious method with random jitter injection.For the circuit design, the design principles of PLL modules are summarized and detail circuits are given; for the requirements of monolithic integration, it proposes a voltage controlled oscillator circuitry with 8 segment tuning curves and gives the adaptive frequency calibration method; for the fractional frequency output function, a second order digital△Σmodulator with resolution less than 100Hz is proposed, and the procedure from the system model to the implementation of Verilog code is also given.Finally, a monolithically integrated fractional-N frequency synthesizer is achieved in SMIC 0.35μm Mixed-signal 2P3M CMOS process. Test results show that this work can flexibly and accurately output the desired frequency, the RMS jitter of fractional frequency output is less than 30ps, conforms to the audio codec 97 (AC'97) 'standards; applied to a 24-bit audio Codec system, it meets the requirements that the SNR of DAC can be up to 100dB and the SNR of ADC is able to achieve 95dB.