A Applied To The Rfid Reader Transmitter 10 Analysis And Design Of Low-power Dac

A 10-bit low power CSDAC (Current-Steering Digital-to-Analog Converter) to be implemented in SMIC 0.13um mixed signal 1p8m 1.2V CMOS process with sampling frequency of 40MHz is presented here. The designed CSDAC is used in the transmitter in the UHF RFID reader.Current-Steering Architecture is favored here in order to meet the sampling speed requirement. Segmentation of 60%(binary weighted form for 4 fine bits and unary form for 6 coarse bits) is chosen here in order to optimize area and power consumption. For the analog part, detailed theoretical analysis is made for the error mechanism of CSDAC which deteriorate the overall performance first. And proper dimensioning of the transistor size is made in order to reduce the error as much as possible. For the digital part, a Latch-SRD(swing reduced device)-Mux combination is used to reshape the control signal of the current cell switch, thus suppressing the output spike during the transition of the control signal.As the highlight of the design, new structures are used to substitute for the conventional ones in parts of the whole circuit, successfully reducing the area and power consumption of the CSDAC.The most effective way to reduce the power consumption of the analog part is to reduce the LSB current, which is constrained by the gate area requirement for small mismatch and the transistor size limitation by the specific CMOS process. A half-LSB current source structure is presented here, managing to reduce the LSB current by half without affecting the mismatch requirement and violating the limitation rules of the specific process. And as a result, the area and power consumption of the current source array is reduced almost by half.One way to reduce the power consumption for the digital part is to lower the complexity of the decoder. A combination of the conventional thermometer decoder and the pseudo decoder is used to compose the coarse bits decoder. The designed decoder integrated the fantastic monotonic transition characteristic of thermometer decoder with the simplicity of pseudo decoder in topology. The thermo-pseudo decoder not only preserves the high linearity thanks to the high three thermo-decoded bits, but also is simplified by the low three bits of pseudo-decoding. The designed decoder is managed to optimize area and power consumption by reducing the number of logic gates composing the decoder by 35% compared to the conventional row-column thermo-decoder structure.In the last part, pre-simulation of the overall CSDAC is made with the help of Cadence-Spectre simulator and data processing ability of Matlab. From the simulation results, we get that DNL and INL are both below 0.5 LSB which satisfy the static performance requirement. And the spurious-free dynamic range (SFDR) is better than 69db with an input signal of 4MHz when the CSDAC is clocked at 40MHz, showing good dynamic performance together with a SNDR over 64db. The total current consumption is 2.95mA which means a low power CSDAC design is achieved.