Cmos Process To Improve The Dram Hold Time

DRAMs are the technology drivers of high volume semiconductor fabrication processes for new generation products that, in addition to computer markets, are finding increased usage in automotive, military and space, telecommunications, and wireless industries. The demands of DRAM are increasing rapidly along with the fast development of the computer in recent years. A new generation of high density and high performance DRAM is requested to meet the advanced applications.DRAM stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades even the power is on unless the capacitor charge is refreshed periodically. Improve the data retention time can reduce the refresh frequency which can dramatically decrease the power dissipation. It becomes more challenge to get better data retention performance than previous generation following the DRAM cell size scaling down because it request not only the same level capacitance with small size but also better leakage performance with small devices.The topic here is to improve the DRAM data retention time in 0.13um CMOS process. In order to make the capacitor with more capacitance, we studied deeply the characteristic of AL₂O₃ which has higher dielectric constant than traditional material of Oxide-Nitride-Oxide, we successfully applied this material in the process by using ALD(Atomic Layer Deposition) which is a new technology developed in recent years. We also did many researches to decrease the depletion layer of the capacitor to increase the capacitance. We employed two different dielectric materials to fabricate 2K height capacitor by dry etch and wet etch without damaging the top area of the capacitor. We focused on reducing the junction leak and sub-threshold leak to improve the device leakage performance. We developed a novel DRAM cell transistor with asymmetric source and drain junction profiles which can dramatically reduce junction leak and suppress the short channel effect. We also successfully used process dynamic adjust to get stable threshold voltage which can get good performance of sub-threshold leakage.By increasing the capacitance and suppress the junction and sub-threshold leak, we finally improved our 0.13um DRAM data retention time around 350ms to 400ms which is more than 100ms better than traditional DRAM.