Design And Implementation Of A Soft Error Rate Estimation Model In Logic Circuits

Types of microprocessors and microcontrollers which are based on digitalintegrated circuits are widely used in various sectors of society and are in the center ofinformation collection and processing. The reliability of integrated circuits has becomean important factor in the working of the whole system because of the importance andthefoundation,especiallyintheaerospaceandmilitaryapplications.When high-energy particles hit semiconductor materials, the charge that is createdwillbecollectedbythesensitiveareaofthetransistor.Ifthecollectedchargeisenough,the single event effects that result from charge collection will temporarily change thelogic value of the node, causing a soft error. With the upgrading of integrated circuitstechnology, the soft errors have become a major factor in the reliability of the circuit.Compared with the memory circuit, the soft error rate in logic circuits has been at arelatively low state. When circuit technology is entering nanometer scale, the soft errorrate in the logic circuits increased rapidly, and there is a trend that will exceed the softerrorrateinthememorycircuit.In this paper, aiming at the soft errors in integrated circuit, the formationmechanism of soft error and the assessment and mitigation methods are described, thegeneration and estimation methods of soft errors in logic circuit are studied, a model isproposedtoestimatethesofterrorrateinlogiccircuit.The logic circuit soft error rate estimation model proposed in this paper which isbased on the process of soft errors occurring, analyses the occurring, propagation andcapturing of the transient pulse that induced the soft errors, using of the logic maskingeffect, electrical masking effect and window masking effect which are inherent in thelogiccircuitstodeterminethesensitizedpathtospeedupthecalculation.The proposed model can obtain the circuit topology information from the netlistfile, can quickly and accurately calculate the critical charge that is necessary for softerroroccuringineachlogical nodeaccordingtothesizeoflogicgateinformationinthecircuit, calculating soft error rate of the circuit which is under a certain radiationenvironment. The proposed model analyses the generation of soft error and the area ofsensitiveregionatthetransistor-levelandhastheaccuracyoftransistor-levelanalysis.In this paper, the proposed evaluation model is implemented, and a set of testcircuitsisselectedforsimulationanalysis.Circuitsimulationresultswellreflectthesofterror rates of the various test circuits, and analyses the test circuits, obtaining thestructureinformationofthecircuitsandthedistributionofsofterrorsinthecircuits.