.65 Nm Input And Output Unit Library Research And Development

The cell library is an important part in the development of integrated circuits, since it contains all fundamental cells to construct ICs. Because of its compatibility and reusability, cell library has been widely adopted to shorten design cycle of ICs. In the cell libraries, the input/output cells (I/O) provide connection between chip and package. Thus, the I/O cells are used to provide driving current, to receive input signals and to provide ESD protection for internal circuits. I/O cell is the one and only one which every chip must use.As the feather size shrinks with the advanced complementary metal-oxide-semiconductor (CMOS) technology, the circuit functions become more complex and the operating frequency becomes higher. However, thinner gate-oxide in nanometer scale CMOS technology has become a great challenge for T/O cells ESD design. To develop T/O with both good performance and high ESD robustness in a limited layout size has been a meaningful topic.In this thesis, an I/O cell library is designed with 65nm CMOS technology. The I/O cell library includes the I/O cells, power cells, and power split cells. The I/O cells have various function types to choose from, including input cells, output cells and bi-directional cells. In the I/O cells, different output stages could be chosen to provide different driving currents, including 2mA,4mA,8mA,12mA,16mA and 24mA. Besides, the T/O pads can be pulled to logic high or low under the tri-state. In input stage, a Schmitt-trigger is available to increase noise margin of input signals. In the proposed I/O cell library, RC clamp is adopted as ESD protection structure, which can provide fast and effective ESD protection in nanometer technology. The layout size of this I/O cell library is very competitive as 30um in width and 188um in height each.The proposed I/O 1 i brary has been developed i n SMIC 65nm CMOS process. Main work including circuit design, simulation, testchip design and testing have been done in this thesis. Testing results have successfully verified all expected functions provided in the T/O cell library, including receiving input signals and transmitting output signals under 100 MHz frequency, logic control and whole chip ESD protection. The ESD performance has been achieved a high protection level as HBM>8.OKV and MM>375V.