Design Of Standard I/O Cell Library In 65nm Process

In this paper, the author is intent to design and verify a set of I/O cells library, including digital I/O unit, analog I/O unit, power unit and power cut off unit. In the output part, it turn output signal with 1.2V to 2.5V by level shifter, and optimizes its structure to improve its working frequency. Besides, the output part also has the current drive capability. In the input part, it adds the Schmitt trigger function, improves its anti-noise capability to input signal, and designs a module with good high voltage tolerance to prevent the output inverter from generating leakage current for the hign voltage in PAD. It also designs a step module to shift the 2.5V input signal to 1.2V for inner circuit use. Furthermore, it add Power-on detection circuit and pull-down circuit, to prevent I/O units from generating leakage current at the time of power-on. In the terms of ESD, it improves the ESD protection circuit between input pins and power, VDD power line and VSS power line. It adopts the resistance and capacitor clamp circuit which is triggered by frequency, and lead in the power cut off unit, isolating the noise interference between digital power and analog power, meanwhile, enhancing the entire ESD protection capability. This I/O cells library is taped out in SMIC 65nm CMOS processing. After tape-out, the author tests and verifies the chip, and the results indicate that this I/O cells library meets the design requirement and passes the industrial standard.