Some Key Technologies Of Soc In Back-end Design

With the continuous development of technology, integrated circuits has enteredthe ultra-deep sub-micron era of SoC, the scale of design is becoming more andmore large, single-chip SoC integration has also reached millions gates. However,development has also brought new challenges. On the one hand, because thedemand of circuit operating frequency has become more and more high, and theresulting power consumption issues must be the important content of a newgeneration SoC design methodology; the other hand, the raise of integration hasbrought additional challenges to the test vector generation, effectively testing to SoCchips become more difficult, therefore, we must adopt some DFT technology toimprove test coverage rate, to ensure design quality. This paper mainly studiesbackend low-power SoC designs in the layout and routing technology, back-endlow-power design methodology, design for testability methods, and brings theresearch results into practice through an example of G.722.2 speech SoC.This paper firstly analyzes the main power source of CMOS circuits, studiesthe theory of low-power design techniques and implementation methods in detail.We learn that general power distribution of G.722.2 speech SoC through doingpower analysis on it. Then, use different low-power techniques such as clock gating,operand isolation, memory block access to different parts of the design, andsuccessfully achieve the purpose of reducing power consumption.The paper studies DFT techniques and test vector generation techniques. Thispaper adapt some scan test techniques to complete the DFT design of G.722.2speech SoC with DFT Compiler, and complete the test vector generation using withTetraMAX. By static timing analysis and formality verification to G.722.2 speechSoC, we ensure that the design's function and timing are both reliability.The paper studies backend layout, routing technology and related theories ofsignal integrity. Physical design of G.722.2 speech SoC has been completed withSoC Encounter, including place and route, power supply planning, clock treesynthesize and detailed layout, design rule verification and so on. Then, to ensurethe design can meet the demand of signal integrity, we also do cross-talk analysisand IR drop analysis, achieve the fully functional, timing correct reliability design,and obtain the GDSII layout data which should be used to tape out.