Research On A High Speed Fft Processor With Fpga

Digital Signal Processing is one of the subjects expanding rapidly in the field of information science during the past several decades.At present,It has applied extensively in many subjects such as communications,radar,sonar,speech and image processing algorithms,programming DSP for general purpose,ASIC and DSP chipset with invariable function for special purpose,FPGA that can be programmed by user.With the development of micro-electronics technology, realizing digital signal processing with FPGA develops rapidly, more and more,FPGA is used in the arithmetic of front-end digital signal processing in place of ASIC and DSP.The theory of FFT algorithm has being mature.Timing control is a difficulty and key to implement the FFT, which should make the whole system work coordinately, also must accord with speed. FFT IP core has been developed and manufactured by international famous FPGA supplier,which has excellent performance but its price is high. In our country, many companies and academy also concentrate on the research and development based on FPGA,gap still exists comparing the performance and speed although progress and development has been made. This subject is requested to use Xilinx FPGA to design a high-speed FFT processor for a SAR echo signal simulator.First, the paper elaborates the theoretical foundation of digital signal processing and principle of FFT.Then it compares the difference among the different algorithm and selects the DIT radix-4 algorithm to design the FFT processor. On this basis,Combination of butterfly flow diagram,it discusses several different hardware architecture of the FFT processor:Sequence structure,Pipelined structure, Parallel architecture,Array structure,Cascade structure.It designs an improved cascade structure to integrate system performance and hardware resources.The complex multiplier in traditional FFT processor is substituted by the XtremeDsp Slice of Virtex-4.This module works at 500 MHz frequency.It can carry on the high speed multiplication computation. The radix-4 butterfly unit adopts 3 levels pipeline structure and 4 parallel data are used in FFT processor.The entire core module applies the combination of pipeline and parallel architecture.Between one step to another, the receiver block applies the structure of pingpang RAM.The controller is designed with Verilog based on FSM (Finite State Machine), which controls effectively memories,butterfly-calculation and Rom.Finally,the 256-point FFT is simulated.Simulation shows the calculation speed and the results basically reach the requirements of the system.