Design And Implementation Of Scalable FFT/IFFT Processor Based On FPGA

With the rapid development of electronic and integrated circuit technology, digitial signal processing has been widely applied in various fields, such like communication system, signal processing, biomedical engineering, autocontrol engineering and so on. Discrete Fourier transformer (DFT) and its fast algorithms as a basic transform in digtial signal processing also have been widely used.It has been more than forty years since FFT algorithm firstly presented, the theory of FFT algorithm is much mature today, but the method of how to implement it is still worth discussing. The real-time computation of FFT with high-speed and large capacity of data flow can be realized by parallel data processing or multilevel pipeline processing. It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.In this thesis, after analyzing two kinds of FFT algorithms, the mixed radix decimation in frequency FFT algorithm has been chosen to realize the FFT processor, also a high speed and scalable pipeline architecture is proposed. This design finishes simulation and synthesis of the system on Stratix II EP2S60F672C3. The simulation indicates that the result of calculation can reach equivalent precision and the operation speed of FFT can satisfy the request of commonly real-time signal processing.