Design And Implementation Of Mixed Radix FFT Processor On FPGA

In high-precision and high-resolution radar imaging systems,the Fast Fourier Transform?FFT?algorithm has been widely used because of its high signal-to-noise ratio.It is of great practical significance to accelerate the execution speed of FFT operations.In this dissertation,a one-dimensional and two-dimensional mixed architecture multi-radix FFT processor is designed based on heterogeneous multi-core SoC.The design is verified by Xilinx Virtex7 FPGA.The results show that the designed FFT processor is correct and meet system design requirements.The main research work of this dissertation is as follows:1.Research and analysis of various algorithm principles and complexity of FFT,and one-dimensional?two-dimensional hardware implementation structures.Considering the performance of the FFT processor,this design selects radix-2,radix-3 and mixed radix algorithms are implemented as implementation algorithms,using one-dimensional sequential recursion?parallel iterations and two-dimensional mixed hardware architecture as the implementation architecture.2.In the mixed radix FFT processor of this design,the butterfly operator is a reconfigurable butterfly operator,which multiplexes the adders and the multipliers,and can be configured by the controller as two parallel radix-2butterfly operators or a radix-3 butterfly operator to save hardware resources.The corresponding conflict-free address rules are designed to optimize RAM storage resources.3.This design has built a hardware test system on Xilinx's XC7V2000T FPGA chip.The FPGA hardware test results of this design shows that the design supports radix-2,radix-3 and mixed radix FFT transform.For single-precision floating-point numbers,and the execution speed reaches the theoretical period value under the given number of butterfly multipliers.For single-precision floating-point numbers,mixed radix FFT processor provides a result accuracy of 10^-5.