The Research And FPGA Implementation Of Blind Multiuser Detection Algorithm In CDMA System

Multiuser dectection is key technology of Third Gneration Mobile Communications, Traditional detection methods is regard as multiple- access interference (MAI) to noise, it can not make use of multi-user information, thereby it reduce the communication quality and system capacity. Whereas Multiuser detection(MUD) technology can effectively overcome the distance effect (Near-Far Effect), and increase system capacity through the use of adequate cross corelations among spreading codes of users todegether signals. However, sent train sequences has been seriously restricted the real-time character and practicality multiuser detection technology. Blind multiuser detection technology can detect the exptected user with only needing the spreading codes and without train sequences and without information of users. So it has attcched much considerable attention and significant research. In view of implementation, how to choose the appropriate algorithm and the ways to meet the requirements of real-time detection and better cost?The major work on this paper is surmmarized as follows:(1)A brief review principles and characteristics of CDMA spread spectrum communication system, analyze the measures of overcoming MAI. A the necessity,the advantages and disadvantages of multi-user detection technology, and deduce several common formulas of multi-user detection algorithm.(2) Mainly research on the LMS blind multi-user detection algorithms and ADALINE, According with the two kinds of algorithms, put forward a new kind of Blind detection algorithm, the algorithm better performance than the traditional LMS algorithm.(3) Describle detailedly of the principles, the whole process characteristic of FPGA, according with its own characteristic of blind multi-user detection, selectothe chip of Xlinx's 4vsx55ff668-12 with FPGA, select ISE as a development environment, XST as synthesis tools, Modelsim as simulation tools. During the course fo hardware implemention, firstly describle functions and modules division of the system; then encode each module with Verilog HDL, and obtain synthesis report, synthesis with XST ,and simulate on function and timing and obtain figure of Modelsim According wihth the requirements of the specific algorithm systems, integrate a systems ,at last obtain the synthesis report of system , and obtain figure of Modelsim timing simulatione , synthesis report and simulation results show that: the design with use of DSP48 module called DSP48IP is much better performance than ordinary 18×18 multipliers design, it solve critical path with parallel processing and the pipelining technology in the overall design,then the clock frequency has much improved than the traditional methods, have good performance and make full use of hardware resources, accuracy of data .According with ethe characteristics of each data and data calibration ,it improved data accuracy in the same hardware resources circumstances.