Study On Implementation Of A Scalable Length And High Speed FFT Processor Based On FPGA

DFT(Discrete Fourier Transform) is the most important fundamental operations and plays a core role in all sorts of digital signal processing. FFT(Fast Fourier Transform) algorithm has achieved a dramatic increase in the efficiency of computation of the DFT, which is widely used in the domains of wireless communication, speech recognition, image processing, and spectrum analysis. As OFDM(Orthogonal Frequency Division Multiplexing) technology appears, different OFDM systems need FFT operation of different lengths, It is more and more important to implement high-speed and scalable length FFT.In this paper, the architecture of scalable length and high speed FFT processor based on FPGA(Field Programmable Gate-Array) is proposed, including the pipeline architecture of the radix mixed FFT algorithm, the address regularity of the read-then-write RAM, the array architecture of short-length FFT and the pipeline complement architecture of CORDIC(Coordinate Rotation Digital Computer) algorithm. According to the architecture of design, the implementation of a scalable length and pipeline-processing FFT processor and its function verification platform are presented.The implementation result of FFT processor indicate:(1)As the FPIC(Field Programmable Integrated Circuit) technology is developed, the device of larger scale and more kind will reduce the cost of designs and applications based on FPIC. Designs on a chip of FPGA, a representative FPIC device, must be popular in more and more domains and products, especially in digital system products. It's produced in small amount, and updated in short time. Recent CPLD(Complex Programmable Logic Device)/FPGA technology is an ideal tool for development and fast prototyping of FFT.(2)The real-time computation of FFT with high-speed and large capacity data flow is realized by parallel processing architecture and multilevel pipeline processing architecture in VLSI(Very Large Scale Integration). It's easy to implement the scalable FFT based on multilevel pipeline processing architecture in FPGA/CPLD.(3)According to the contradistinguish of all kinds of FFT processing architecture, the design thoughts, rule, method, the characteristics of radix mixed FFT algorithm meets the requirements of scalable FFT architecture. The other FFT algorithms havetheir own limitations.(4)In order that the design is appropriately synthesized and laid out in FPGA, it's necessary to adapt the underlying algorithm and to optimize the design to suit the facilities of data processing made possible by FPGA/CPLD, such as CORDIC algorithm for the twiddle factor multiplication and such as the complement pipeline architecture of CORDIC processor.(5)There is a rule of the address of the read-then-write RAM, which directs the change of the scalable FFT architecture, and it's found in the abstract.(6)The experimental result of FFT processor indicate: The theories of functional module are correct, and their architectures are fair enough. The experiment result indicates that the computation time of 1024-point FFT is 52us when the frequency system clock is 40 MHz and the rate of data is 20MHz.