As the development of technology, high-performance interconnection network technology has become the key factor of high-performance computer systems.The high-radix routers and high-radix network gradually become the mainstream of the development of high-performance interconnect network. Therefore, the analysis and design of high-radix routers and high-radix network are particularly important. This thesis mainly study high-radix routers and high-radix interconnection network that TH2super computer system may be used. We get rich and detailed performance evaluation data for high-radix routing chip design and the actual system planning.We introduce the existing high-radix routers and high-radix network and analysis of the key factors that affect the performance of the interconnection network. We describe several typical high-radix network topology, in-depth study of delay and throughput of the high-radix network of k-ary n-cube provide a theoretical basis for the performance evaluation of high-radix network topology. We introduce TH2high-radix router architecture. By building balanced traffic model, exponential traffic model, hot-spot traffic model and VC burst traffic model in NC Verilog environment, we evaluate NoC performance of TH2high-radix router which based TILE, and analysis of the throughput and latency of NoC. We study of the NoC-based dynamically allocated multi-queue (DAMQ) buffer management mechanism packet scheduling algorithms and flow control strategies, focusing on the DAMQ stress tests under different traffic models which provide a reference for DAMQ depth design, optimum performance credit threshold setting.For the requirements of high-radix routers FPGA verification, we design the on-chip integrated virtual excitation source with pseudo-random binary sequence (PRBS) PRBS-31originality and design a dynamic connection end-to-end reliable transport protocol used to verify the correctness of the high-radix routing chip adaptive routing strategy. Further analysis carried out in high-radix network performance. We comparative analysis of the Mesh and Mesh-Tree and the high-radix Mesh network performance of delay and throughput. Analysis of the high-radix routing chip injected port number and the number of links on each dimension of high-radix network which influence of the performance of high-radix network. And get the best performance ratio of the number of ports and the number of interconnection links. The process which we evaluate the large-scale interconnection network performance based on Verilog can be used as the basis of analysis of other high-radix network and provide a new perspective and method for large-scale network performance evaluation. |