Based Fpga Variable Point Fft Processor Design And Realization

FFT is a fast algorithm of DFT and is one of the core technologies to Digital Signal Processing, which is widely applied to voice sounds, audio frequency, image processing, information system, control and instrument, geological exploration, aeronautics and astronautics, biomedical designing and other fields. Different application fields need FFT processor with different properties. Especially after the OFDM and OFDMA technologies appeared based on alterable point FFT, the research of alterable point FFT processor has important practical significance.This article designed and realized the alterable point FFT processor based on FPGA and used the mixed-radix algorithm which is mixed sampled by radix-16 and the radix-2/4/8 in frequency. This design has the following characteristics: firstly, optimally realized the radix-16 butterfly calculation unit by using two level of radix-4 butterfly calculation unit, and solved the question that the structure is complex and it takes hardware excessively when directly transformed the radix-16 butterfly calculation formula to the hardware; secondly, realized the alterable radix-r butterfly calculation unit(r=2,4,8) by using the first-level radix-4 butterfly calculation unit and the first-level radix-2 butterfly calculation unit; thirdly, According to computation characteristics of the different points' FFT, and through the different starting value, the length of stride and the rule arrangement cnt, designed and realized the address generation and the control unit in variable point FFT processor. We made use of the cascade processing structure and the modular thought in the FFT processor, and used the high efficiency complex number multiplication processors and the RAM structure of Ping-Pong, raised the processing speed and realized the point which is operated by the FFT processor can be variable. This design takes FPGA chip Cyclone II EP2C50U484C8 as the hardware platform and Quartus II as the software platform, uses the VHDL hardware description language to realize the alterable point FFT processor that is able to satisfy the four kind of request that FFT transformation points respectively is 128, 512, 1024 and 2048 in the IEEE 802.16eOFDMA system. The clock frequency of the designed FFT processor synthesized by Quartus II reaches more than 100MHZ, which meets the demand of real-time signal processing. The simulating test results by using Modelsim and Matlab simulation soft wares proved that the designing was correct. Because of using cascade structure and the modular thought, the designed FFT processor can be easily extended to many application situations of integer order power whose points number is 2.